Efficient Memory Partitioning in Software Defined Hardware
As programmers turn to software-defined hardware (SDH) to maintain a high level of productivity while programming hardware to run complex algorithms, heavy-lifting must be done by the compiler to automatically partition on-chip arrays. In this paper, we introduce an automatic memory partitioning system that can quickly compute more efficient partitioning schemes than prior systems. Our system employs a variety of resource-saving optimizations and an ML cost model to select the best partitioning scheme from an array of candidates. We compared our system against various state-of-the-art SDH compilers and FPGAs on a variety of benchmarks and found that our system generates solutions that, on average, consume 40.3% fewer logic resources, 78.3% fewer FFs, 54.9% fewer Block RAMs (BRAMs), and 100% fewer DSPs.
Code (0)
등록된 구현이 없습니다.
Similar Papers 제목 키워드 기반
HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation
Tensor computations overwhelm traditional general-purpose computing devices due to the large amounts of data and operations of the computations. They call for a holistic solution composed of both hardware acceleration an…
Bayesian OptimizationQ-LearningEnergy Efficient Software Hardware CoDesign for Machine Learning: From TinyML to Large Language Models
The rapid deployment of machine learning across platforms from milliwatt-class TinyML devices to large language models has made energy efficiency a primary constraint for sustainable AI. Across these scales, performance …
Hardware-conscious Hash-Joins on GPUs
Traditionally, analytical database engines have used task parallelism provided by modern multi-socket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerator…
CPUGPUHardware Software Co-design of Statistical and Deep Learning Frameworks for Wideband Sensing on Zynq System on Chip
With the introduction of spectrum sharing and heterogeneous services in next-generation networks, the base stations need to sense the wideband spectrum and identify the spectrum resources to meet the quality-of-service, …
compressed sensingA TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching
Modern mobile CPU software pose challenges for conventional instruction cache replacement policies due to their complex runtime behavior causing high reuse distance between executions of the same instruction. Mobile code…