Frequency-Dependent Power Consumption Modeling of CMOS Transmitters for WNoC Architectures
Wireless Network-on-Chip (WNoC) systems, which wirelessly interconnect the chips of a computing system, have been proposed as a complement to existing chip-to-chip wired links. However, their feasibility depends on the availability of custom-designed high-speed, tiny, ultra-efficient transceivers. This represents a challenge due to the tradeoffs between bandwidth, area, and energy efficiency that are found as frequency increases, which suggests that there is an optimal frequency region. To aid in the search for such an optimal design point, this paper presents a behavioral model that quantifies the expected power consumption of oscillators, mixers, and power amplifiers as a function of frequency. The model is built on extensive surveys of the respective sub-blocks, all based on experimental data. By putting together the models of the three sub-blocks, a comprehensive power model is obtained, which will aid in selecting the optimal operating frequency for WNoC systems.
Code (0)
등록된 구현이 없습니다.
Similar Papers 제목 키워드 기반
A $0.11-0.38$ pJ/cycle Differential Ring Oscillator in $65$ nm CMOS for Robust Neurocomputing
This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing th…
An Integer-N Frequency Synthesizer for Flexible On-Chip Clock Generation
A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in 65 nm CMOS technology. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and…
Power Modeling in mm-Wave and Terahertz CMOS Transmitters for Wireless Network-on-Chip
Wireless Network-on-Chip (WNoC) systems, which interconnect chips using wireless links, face significant challenges in area and power consumption. To tackle these constraints, behavioral models (BMs) are crucial for asse…
A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing
Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are i…
Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing
We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate t…