paper-with-me

홈 › Papers

Iterative Circuit Repair Against Formal Specifications

2023-03-02 · Matthias Cosler, Frederik Schmitt, Christopher Hahn, Bernd Finkbeiner

We present a deep learning approach for repairing sequential circuits against formal specifications given in linear-time temporal logic (LTL). Given a defective circuit and its formal specification, we train Transformer models to output circuits that satisfy the corresponding specification. We propose a separated hierarchical Transformer for multimodal representation learning of the formal specification and the circuit. We introduce a data generation algorithm that enables generalization to more complex specifications and out-of-distribution datasets. In addition, our proposed repair mechanism significantly improves the automated synthesis of circuits from LTL specifications with Transformers. It improves the state-of-the-art by $6.8$ percentage points on held-out instances and $11.8$ percentage points on an out-of-distribution dataset from the annual reactive synthesis competition.

📄 PDF Abstract BibTeX arXiv:2303.01158

Code (1)

reactive-systems/circuit-repair 공식 구현 tf

Tasks

Representation Learning

Methods 이 논문이 사용한 방법론

Attention 설명 없음
Repair 설명 없음
Linear Layer A Linear Layer is a projection $\mathbf{XW + b}$.
Absolute Position Encodings Absolute Position Encodings are a type of position embeddings for [Transformer-based models] where positional encodings are…
Label Smoothing Label Smoothing is a regularization technique that introduces noise for the labels. This accounts for the fact that datasets may have mistakes in them, so maximizing the…
Softmax The Softmax output function transforms a previous layer's output into a vector of probabilities. It is commonly used for multiclass classification. Given an input vector $x$…
Adam 설명 없음
Layer Normalization Unlike batch normalization, Layer Normalization directly estimates the normalization statistics from the summed inputs…

Similar Papers 제목 키워드 기반

Natural Synthesis: Outperforming Reactive Synthesis Tools with Large Reasoning Models

2026-05-14 · Frederik Schmitt, Matthias Cosler, Niklas Metzger, Julian Siber 외 arxiv

Reactive synthesis, the problem of automatically constructing a hardware circuit from a logical specification, is a long-standing challenge in formal verification. It is elusive for two reasons: It is algorithmically har…

AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs

2025-08-04 · Yao Lai, Souradip Poddar, Sungyoung Lee, Guojin Chen 외 arxiv

Despite recent advances, analog front-end design still relies heavily on expert intuition and iterative simulations, which limits the potential for automation. We present AnalogCoder-Pro, a multimodal large language mode…

CktFormalizer: Autoformalization of Natural Language into Circuit Representations

2026-05-08 · Jing Xiong, Qi Han, Chenchen Ding, He Xiao 외 arxiv

LLMs can generate hardware descriptions from natural language specifications, but the resulting Verilog often contains width mismatches, combinational loops, and incomplete case logic that pass syntax checks yet fail in …

Automated Repair of Declarative Software Specifications in the Era of Large Language Models

2023-10-19 · Md Rashedul Hasan, Jiawei Li, Iftekhar Ahmed, Hamid Bagheri

The growing adoption of declarative software specification languages, coupled with their inherent difficulty in debugging, has underscored the need for effective and automated repair techniques applicable to such languag…

VeriAct: Beyond Verifiability -- Agentic Synthesis of Correct and Complete Formal Specifications

2026-03-31 · Md Rakib Hossain Misu, Iris Ma, Cristina V. Lopes arxiv

Formal specifications play a central role in ensuring software reliability and correctness. However, automatically synthesizing high-quality formal specifications remains a challenging task, often requiring domain expert…