PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer
Prefix adders are widely used in compute-intensive applications for their high speed. However, designing optimized prefix adders is challenging due to strict design rules and an exponentially large design space. We introduce PrefixGPT, a generative pre-trained Transformer (GPT) that directly generates optimized prefix adders from scratch. Our approach represents an adder's topology as a two-dimensional coordinate sequence and applies a legality mask during generation, ensuring every design is valid by construction. PrefixGPT features a customized decoder-only Transformer architecture. The model is first pre-trained on a corpus of randomly synthesized valid prefix adders to learn design rules and then fine-tuned to navigate the design space for optimized design quality. Compared with existing works, PrefixGPT not only finds a new optimal design with a 7.7% improved area-delay product (ADP) but exhibits superior exploration quality, lowering the average ADP by up to 79.1%. This demonstrates the potential of GPT-style models to first master complex hardware design principles and then apply them for more efficient design optimization.
Code (0)
등록된 구현이 없습니다.
Similar Papers 제목 키워드 기반
PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning
In this work, we present a reinforcement learning (RL) based approach to designing parallel prefix circuits such as adders or priority encoders that are fundamental to high-performance digital design. Unlike prior method…
Deep Reinforcement Learningreinforcement-learningReinforcement LearningReinforcement Learning (RL)PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization
Prefix adders are fundamental arithmetic circuits, but their design space grows exponentially with bit-width, posing significant optimization challenges. Previous works face limitations in performance, generalization, an…
Language ModelingLanguage ModellingLarge Language ModelCross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long stu…
Active LearningBIG-bench Machine LearningGraPhSyM: Graph Physical Synthesis Model
In this work, we introduce GraPhSyM, a Graph Attention Network (GATv2) model for fast and accurate estimation of post-physical synthesis circuit delay and area metrics from pre-physical synthesis circuit netlists. Once t…
Graph AttentionmodelPrefixLLM: LLM-aided Prefix Circuit Design
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for…
Text Generationvalid