paper-with-me

Papers

Bayesian Optimization for Macro Placement

2022-07-18 · Changyong Oh, Roberto Bondesan, Dana Kianfar, Rehan Ahmed, Rishubh Khurana, Payal Agarwal, Romain Lepert, Mysore Sriram, Max Welling

Macro placement is the problem of placing memory blocks on a chip canvas. It can be formulated as a combinatorial optimization problem over sequence pairs, a representation which describes the relative positions of macros. Solving this problem is particularly challenging since the objective function is expensive to evaluate. In this paper, we develop a novel approach to macro placement using Bayesian optimization (BO) over sequence pairs. BO is a machine learning technique that uses a probabilistic surrogate model and an acquisition function that balances exploration and exploitation to efficiently optimize a black-box objective function. BO is more sample-efficient than reinforcement learning and therefore can be used with more realistic objectives. Additionally, the ability to learn from data and adapt the algorithm to the objective function makes BO an appealing alternative to other black-box optimization methods such as simulated annealing, which relies on problem-dependent heuristics and parameter-tuning. We benchmark our algorithm on the fixed-outline macro placement problem with the half-perimeter wire length objective and demonstrate competitive performance.

📄 PDF Abstract BibTeX arXiv:2207.08398

Code (0)

등록된 구현이 없습니다.

Tasks

Bayesian OptimizationCombinatorial Optimization

Similar Papers 제목 키워드 기반

Non-Overlapping Placement of Macro Cells based on Reinforcement Learning in Chip Design

2024-07-26 · Tao Yu, Peng Gao, Fei Wang, Ru-Yue Yuan

Due to the increasing complexity of chip design, existing placement methods still have many shortcomings in dealing with macro cells coverage and optimization efficiency. Aiming at the problems of layout overlap, inferio…

Macro Placement by Wire-Mask-Guided Black-Box Optimization

2023-09-21 · NeurIPS 2023 11

The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important sub…

On Joint Learning for Solving Placement and Routing in Chip Design

2021-10-30 · NeurIPS 2021 12 · Ruoyu Cheng, Junchi Yan

For its advantage in GPU acceleration and less dependency on human experts, machine learning has been an emerging tool for solving the placement and routing problems, as two critical steps in modern chip design flow. Bei…

GPUreinforcement-learningReinforcement LearningReinforcement Learning (RL)

Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution

2026-06-08 · Shibing Mo, Jing Liu, Jianchu Xu, Ruilin Wu arxiv

Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in mac…

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

2026-08-13 · Ruogu Chen, Jie Han arxiv

Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows …