LUCAS: A CMOS-Based Fast Readout ASIC for Silicon Photomultipliers -- Measurement and Performance Evaluation
This paper presents the design, implementation, and performance evaluation of LUCAS, a low-power, ultra-low jitter ASIC optimized for SiPM readout in Time-of-Flight Computed Tomography (ToF-CT) applications. Leveraging a novel preamplifier design with low input impedance and current-mode operation, LUCAS addresses challenges such as parasitic capacitance of SiPMs and high-speed detection requirements. The ASIC, fabricated in TSMC 65nm CMOS technology, features eight channels with an integrated preamplifier and comparator, achieving an SPTR of 201 ps FWHM at 3.2 mW/ch. Experimental validation includes input impedance measurements, SPTR testing with a pulsed laser source, and energy-to-Time-over-Threshold calibration using monoenergetic X-ray sources. The results demonstrate the effectiveness of LUCAS in enhancing timing resolution while minimizing power consumption, offering significant advancements for high-resolution ToF-CT imaging.
Code (0)
등록된 구현이 없습니다.
Similar Papers 제목 키워드 기반
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and e…
High Performance Three-Terminal Thyristor RAM with a P+/P/N/P/N/N+ Doping Profile on a Silicon-Photonic CMOS Platform
3T TRAM with doping profile (P+PNPNN+) is experimentally demonstrated on a silicon photonic platform. By using additional implant layers, this device provides excellent memory performance compared to the conventional str…
Vision Transformer Accelerator ASIC for Real-Time, Low-Power Sleep Staging
This paper introduces a lightweight vision transformer aimed at automatic sleep staging in a wearable device. The model is trained on the MASS SS3 dataset and achieves an accuracy of 82.9% on a 4-stage classification tas…
Sleep StagingDesign and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
Edge neuromorphic systems need compact, configurable hardware that combines probabilistic inference, local learning, and an interface to emerging analogue memory. We present four interface-compatible digital IP blocks im…
Silicon Photonic Architecture for Training Deep Neural Networks with Direct Feedback Alignment
There has been growing interest in using photonic processors for performing neural network inference operations; however, these networks are currently trained using standard digital electronics. Here, we propose on-chip …